1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a semiconductor memory device having a word driver circuit based on a divided decoding system.
2. Description of the Related Art
Semiconductor memory devices have become highly integrated as fine processing technology has improved. In particular, the dynamic random-access memory (hereinafter referred to as DRAM) of a simple memory cell structure has become highly integrated. As a result, 16 Mbit DRAMs sample have begun to be distributed to users, and papers, on 64 Mbit DRAMs are even being read in advanced groups such as academic societies.
In 16 Mbit DRAMs, the internal voltage is decreased to protect against deterioration of transistor characteristics and insufficient dielectric strength of gate oxide films and capacity oxide films, which may be caused by hot carriers. Further, in 64 MDRAMs, many products have been announced which are driven by a decreased source voltage of 3.3 V instead of the conventional 5 V in order to meet the above problems and to conserve power.
Semiconductor memory devices of a divided decoding system are proposed to reduce wiring space with a plurality of divided word lines and with drivers provided for each word line for supplying an electric current thereto.
FIG. 1 is a circuit diagram showing the structure of the principal part of a semiconductor memory device of a divided decoding system, while FIG. 2 is a circuit diagram of the word-line-drive-circuit represented by numeral 3a in FIG. 1.
The memory cell array constructed of memory cells MC00 to MCB2 is divided into a plurality of blocks in the direction separating word lines, word-line-drive-circuits 3a to 3d, 4a to 4d, 5a to 5d are disposed on both sides of all blocks, and each word line is connected alternately to word-line-drive-circuits 3a to 3d, 4a to 4d, and 5a to 5d.
Memory cells MC00 to MCB2 are disposed at each of the intersecting points of word lines WL00 to WLB3 and bit lines BL0 to BL5.
Complementary signals XSW0 to XSW2 and XSW0 to XSW2 are output from line decoder 1 to word-line-drive-circuits 3a to 3d, 4a to 4d, 5a to 5d in order to select the word-line-drive-circuit.
Lines for word-line-drive-current-supply-signals RA0 to RA3 are transmitted on word-line-drive-circuits in the direction perpendicular to the word lines. Signals RA0, RA2 are inputted to word-line-drive-circuits 3a, 4a, 5a, 3c, 4c, 5c, and signals RA1, RA3 to word-line-drive-circuits 3b, 4b, 5b, 3d, 4d, 5d alternately, respectively.
Word-line-drive-circuits 3a to 3d, 4a to 4d, and 5a to 5d are composed of two drive circuits of the self-boost type, as shown in FIG. 2 which is used to only transistor's capacities for boosting without installing external capacities.
For example, if complementary signal XSW0 and word-line-drive-current-supply-signal RA0 are selected, N type transistors Q23, Q26 are turned off by signals XSW0 and XSW0, and after the potential of nodes 21, 22 are increased from the ground potential to the potential to be obtained by decreasing the threshold voltages of N type transistors Q22, Q25, respectively, from the source potential, the potential of node 21 is further increased, due to the self-boost of the transistor generated in RA0, to a potential higher than that of RA0 whose potential has been boosted in advance by means of a boost circuit not shown. The potential of word line WL00 is also increased to the same potential as that of RA0. Not only in circuit 3a, but also in circuit 3c, the potential of line WL02 is increased in the same way, and memory cells MC00, MC01, MC02 are selected.
FIG. 3 is a circuit diagram showing the detailed structure of the principal part of the word-driver-circuit which supplies an electric current to a word line in the circuit shown in FIG. 1.
The present example of the conventional type is composed of decoder 21 which is selected by line address signals and a plurality of drivers which drive word lines, and drivers 22, 22' are shown in the figure. This conventional type structure is provided for each word line in the memory cell, but is shown here for only particular word line WL for simplification.
Decoder 21 comprises P type transistors QP21, QP22, N type transistors QN21, QN22, Q23, and inverter INV21, in which the sources of transistors QP21, QP22 are connected to the power source supply line and the drains thereof are connected to node 21. To the gate of transistor QP21, precharge signal .phi.p is input, and to a gate of transistor Q22, the output of inverter INV21 is input. To each gate of transistors QN21, QN22, QN23, a line address signal is inputted, while node 21 is grounded through each transistor QN21, QN22 and QN23 in succession.
Driver 22 (22') is composed of N type transistors QN24, QN25, QN26 (QN24', QN25', QN26'), in which the gate of transistor QN24 (24') is connected to the power supply line, the source thereof is connected to the output terminal of inverter INV21, and the drain thereof(node N22, N22') is connected to the gate of transistor QN25 (QN25'). To the source of transistor QN25 (25'), word-line-drive-signal .phi..sub.a is inputted, and a drain which is connected to word line is grounded via transistor QN26 (QN26'), whose gate is connected to node 21.
Next, the operation of the present example of the conventional type will be described.
When resetting, the ground voltage is applied to precharge signal .phi..sub.p, and node N21 is charged to the source voltage VCC through transistor QP21. When selecting a memory cell, precharge signal .phi..sub.p transits to the source voltage, and each line address signal to be inputted to each gate of transistors QN21, QN22, QN23 is activated to select the decoder.
In the case that decoder 21 is selected by line address signals, each of transistors QN21, QN22, QN23 is turned on to make node N21 have the ground voltage, and node N22 (N22') is charged to the potential of (VCC-VT) by the output of inverter INV21, where VT is the threshold voltage of transistor QN24 (QN24'). Then activated word-line-drive-signal .phi..sub.a causes the voltage of node N22 (N22') to increase higher than that of the VCC by self-boosting of transistor QN25 (QN25'), thereby activating word-line-selection-signal .phi.WL (.phi.'WL) to select the memory cell. In this way, word line WL is activated by an electric current supplied from the source by receiving word-line-selection-signals .phi.WL, .phi.'WL which are output respectively from a plurality of drivers 22, 22' to word line WL.
Voltage VN2 (VN2') of node N22 (N22') is given in the following equation, where CG is the gate capacity of transistor QN25 (QN25')and CL is the load capacity of node N22 (N22'): EQU VN2 (VN2')={(CG.times.V.phi..sub.a)/(CG+CL)}+(VCC-VT) (1)
Since transistor QN25 (QN25') is "on" when VN2 (VN2')-V.phi..sub.2 &gt;VT, thus VCC becomes as follows. EQU VCC&gt;2VT+{1-[CG/(CG+CL) ]}V.phi..sub.2 ( 2)
Therefore, if it is assumed that the capacity ratio of CG:CL=5:1, V.phi..sub.a =4 V, VT=0.8 V, a source voltage VCC of 2.3 V or more is required to turn transistor QN25 (QN25') "on".
In the semiconductor memory device having a word-driver-circuit according to the above conventional divided decoding system, a plurality of word-line-selection-signals .phi.WL (.phi.'WL) selected by decoder 21 are driven by driver 22 (22') provided separately for each word line, and hence transistor QN25 (QN25') which serves as the driving transistor of each driver 22 (22') is required to be made small with a small capacity CG gate. Consequently, when the source voltage is low, the voltage of node N22 (N22') cannot be raised sufficiently and transistor QN25 (QN25') is caused to operate in the saturation region resulting in a slow rise of the word lines.
FIG. 4 is a graph showing the relation among the voltages of node N22, word-line-drive-signal .phi..sub.a and word-line-selection-signal .phi.WL in FIG. 3.
Since the voltage of word-line-selection-signal .phi.WL varies upward and downward corresponding to variations in the voltage of node N22, in the case of a voltage drop of node N22, word-line-selection-signal .phi.WL takes longer to reach the word-line- selection-threshold-voltage which recognizes selection of the word line.
Further, since word lines cannot be activated when the source voltage drops, it is necessary to provide a source voltage high enough to cover the drop which makes the source margin of the system inefficient. When the voltage of node N 22 (N22') is increased by increasing gate capacity CG of transistor QN25 (QN25') for the purpose of avoiding this drawback, transistor QN25 (QN25') becomes large resulting in a remarkably increased chip area of the semiconductor memory device.